Method for determining a reference clock phase form band-limited digital data streams

ABSTRACT

The invention provides a method for recovering a digital datastream ( 301 ), in which a reference clock phase ( 308 ) is recovered from the digital datastream ( 301 ), the digital datastream ( 301 ) being received in a datastream receiver ( 302 ), low-pass filtered in a low-pass filter device ( 303 ), an edge position signal ( 309 ) being determined by comparing an amplitude of the low-pass filtered datastream ( 305 ) with a predeterminable threshold value ( 108 ) in an edge position detection device ( 304 ) and a phase deviation ( 111   a ) being determined from a time difference between a 0/1 threshold intersection point ( 109 ) of the threshold value ( 108 ) with a 0/1 data transition ( 101 ) or a −1/1 threshold intersection point ( 110 ) of the threshold value ( 108 ) with a −1/1 data transmission ( 102 ) and the target time of the control system ( 310 ) in a phase correction device ( 307 ), so that the phase deviation ( 111   a ) can be corrected with the phase correction offset ( 111   b ) in the phase correction device ( 307 ).

[0001] The present invention relates to a method for recovering adigital datastream and, in particular, relates to a method forrecovering a reference clock phase from the digital datastream.

[0002] Datastreams are transmitted, for example, as AMI (Alternate MarkInversion) datastreams. In the AMI data transmission method, two linesare provided without DC component for the transmission of datastreams,the analog signals on one line being inverted with respect to the analogsignals on the other line.

[0003] In the text which follows, logical signals are signals, thesignal level of which changes from one logical state to another logicalstate and the signals can assume a minimum datastream value, a baselinevalue or a maximum datastream value. In this arrangement, the minimumdatastream value is called a logical “−1”, while the value of a baselineis called a logical “0” and the maximum datastream value is a logical“+1”. Between all of these signal values, transitions can take place,i.e. there are 0/1 data transitions, 1/0 data transitions, 0/−1 datatransitions, 1/0 data transitions which will be called single-step datatransitions in the text which follows. Furthermore, there are −1/1 datatransitions and 1/−1 data transitions which will be called double-stepdata transitions in the text which follows.

[0004] The information to be transmitted is digitized in such a mannerthat digital datastreams are provided with a multiplicity of theabovementioned data transitions. The reception and further processing ofdigital datastreams require that a reference clock signal can be deriveddirectly from the digital datastream.

[0005] Conventionally, a clock signal which is derived directly fromdetector data transitions, for example from a baseline value to amaximum datastream value or to a minimum datastream value or,respectively, a transition from a minimum datastream value to a maximumdatastream value or conversely, is provided as the reference clocksignal.

[0006] In practice, the direct recovery of a reference clock from thedatastream is made more difficult by the fact that the received digitaldatastreams have jitter i.e. are generally noisy and have “AMI codeviolations” (bipolar violations).

[0007] Conventionally, for example, a time at which a datastream crossesa fixed threshold is taken as the time of a 0/1 data transition.

[0008] A disadvantage of this conventional method consists in thatbit-pattern-dependent distortion must be avoided, with the consequencethat the frequency spectrum of the datastream must also containfrequency components above a center frequency of the useful signal.

[0009] This leads to the further disadvantage that noise components arealso carried and amplified which can corrupt the useful signal andincrease the phase jitter.

[0010]FIG. 2 shows a conventional method for determining a referenceclock RT from a received digital datastream DS. In a datastream receiverE, a digital datastream DS is received and the received signal issupplied to an edge position detection device F which is supplied with athreshold value from a threshold setting device S. This threshold valuecan be provided as a positive value or as a negative value and the valueis preferably between a minimum datastream value and a maximumdatastream value. If the received digital datastreams supplied to theedge position detection device F exceeds or drops below this thresholdvalue, a threshold intersection point between, for example, a 0/1 datatransition (or another one of the abovementioned data transition) andthe set threshold value is output as the reference clock phase RT.

[0011] Furthermore, disturbances such as jitter, i.e. in general noise,band limiting due to the transmission channel etc. have adisadvantageous effect on the determination of a reference clock phaseRT which, therefore, has large errors in such a conventional method ofdetermination.

[0012] It is thus an object of the present invention to recover areference clock phase from a received digital datastream, wherein anedge position signal obtained must be corrected with the aid of a phasecorrection value in order to obtain an optimum reference clock phasesignal.

[0013] This object is achieved by a method for recovering a digitaldatastream in which a reference clock phase is recovered from a digitaldatastream, according to claim 1, and by a device having the features ofclaim 13.

[0014] The method according to the invention for recovering a digitaldatastream in which a reference clock phase is recovered from thedigital datastream, according to claim 1, and the device having thefeatures of claim 13, has the following advantages.

[0015] Advantageously, a received digital datastream is low-passfiltered in order to eliminate unwanted noise components.

[0016] The core of the invention is a method for recovering a digitaldatastream in which a reference clock phase is recovered from thedigital datastream and an edge position signal obtained is correctedwith a phase correction value as determined by a determination of a datatransition.

[0017] The subclaims contain advantageous further developments andimprovements of the respective subject matter of the invention.

[0018] According to a preferred development of the present invention,the threshold value is set in such a manner that it assumes a valuebetween a baseline value (logical “0”) and a maximum data value (logical“1”).

[0019] According to a further preferred development of the presentinvention, the threshold value is set in such a manner that it assumes avalue between the baseline value and a minimum datastream value (logical“−1”).

[0020] According to yet another preferred development of the presentinvention, the threshold value will be variably adjustable.

[0021] According to yet another preferred development of the presentinvention, the received digital datastream is low-pass filtered with avariable frequency.

[0022] According to yet another preferred development of the presentinvention, an absolute value of a phase correction value is provided independence on a cut-off frequency of the low-pass filtering device andof the data transmission channel.

[0023] According to yet another preferred development of the presentinvention, an absolute value of a phase correction value is provided independence on an adjustable threshold value.

[0024] According to yet another preferred development of the presentinvention, an edge slope of a data transition in the digital datastreamis calculated and the edge is allocated to a preceding data transitionin accordance with the greatest similarity.

[0025] According to yet another preferred development, the trend of thelast control error is used for determining an edge position signal.

[0026] According to yet a further preferred development, the datatransition preceding in each case is used for determining an edgeposition signal of a last detected data transition.

[0027] According to yet another preferred development of the presentinvention, an arbitrary preceding data transition (n−2, n−3, . . . ) isused, n being the last detected data transition.

[0028] According to yet another preferred development, a variablethreshold value is used which is derived from a peak amplitude of thedatastream by multiplying the peak amplitude of the datastream by apredeterminable factor of less than 1.

DRAWINGS

[0029] Exemplary embodiments of the invention are shown in the drawingsand explained in greater detail in the description following.

[0030] In the drawings:

[0031]FIG. 1 shows an eye pattern of a band-limited digital datastreamwith single-step and double-step data transitions;

[0032]FIG. 2 shows an arrangement for recovering a reference clock phasefrom a digital datastream according to the prior art;

[0033]FIG. 3 shows a block diagram of an exemplary embodiment of themethod according to the invention for recovering a reference clock phasesignal from a digital datastream; and

[0034]FIG. 4 shows a block diagram which illustrates the steps neededfor determining a reference clock phase signal, which are performed in aphase correction device according to an exemplary embodiment of thepresent invention.

EXEMPLARY EMBODIMENTS

[0035]FIG. 1 shows an eye pattern of a band-limited digital datastreamwith single-step and double-step data transitions.

[0036] In the eye pattern shown in FIG. 1, a digital datastream can beseen and, for example, data transitions are shown which represent asingle-step 0/1 data transition 101, a single-step 0/−1 data transition103, a single-step 1/0 data transition 103 a, a single-step 1/0 datatransition 10 a, a double-step −1/1 data transition 102 and adouble-step 1/−1 data transition 104.

[0037] The data transitions are represented, for example, as transitionsbetween a baseline value 105 and a maximum datastream value 106 or,respectively, a minimum datastream value 107, or between a minimumdatastream value 107 and a maximum datastream value 106. A variablyadjustable threshold value 108 provides different intersection pointswith data transitions and, for example, two intersection points areshown, a 0/1 threshold intersection point 109 as intersection point of a0/1 data transition 101 with the threshold value 108 and a −1/1threshold intersection point 110 with the double-step −1/1 datatransition 102.

[0038] As can be seen from FIG. 1, the edge slope of the −1/1 datatransition 102 is greater than the edge slope of the 0/1 data transition101. The corresponding intersection points, i.e. the 0/1 thresholdintersection point 109 and the −1/1 threshold intersection point 110correspondingly do not coincide but are apart by a phase correctionoffset 110 on the time axis. The band limiting of the received digitaldatastream results in the eye pattern shown in FIG. 1, the consequencealso being that a distinction must be made between single-step anddouble-step data transitions in order to avoid errors during therecovery of a reference clock phase signal.

[0039]FIG. 3 shows a block diagram of the method according to theinvention for recovering a reference clock phase signal from a digitaldatastream.

[0040] In the block diagram shown in FIG. 3, a digital datastream 301 isreceived by a datastream receiver 302, the output signal of thedatastream receiver 302 being supplied to a low-pass filter device 303.In the low-pass filter device 303, low-pass filtering is performed witha predeterminable cut-off frequency, a cut-off frequency being set insuch a manner that unwanted noise components and noise are filtered outof the useful signal.

[0041] The low-pass-filtered datastream has the characteristicsexplained with reference to FIG. 1, in particular resulting in the eyepattern which can be seen in a representation. The low-pass-filtereddatastream 305 is supplied, on the one hand, to a phase correctiondevice 307 and, on the other hand, to an edge position detection device304. In the edge position detection device 304, an intersection point ofa data transition (single-step or double-step) is compared with athreshold value 108 which can be predetermined by means of a thresholdsetting device 306 and is supplied to the edge position detection device304. The result of the comparison is an edge position signal 309 whichis also supplied to the phase correction device 307. In the phasecorrection device 307, a phase correction is performed. The phasecorrection value 111 is composed of an essentially constant phasecorrection offset 111 b and a variable phase deviation 111 a. The phasedeviation 111 a is the distance between the edge position signal 309 andthe target time of the control system 310.

[0042] The method steps for determining the phase correction value 111are explained below with reference to FIG. 4. As the result of the phasecorrection in the phase correction device 307, a reference clock phasesignal 308 which optimally tracks the received datastream is provided atthe output of the phase correction device 307.

[0043]FIG. 4 illustrates a flow chart which shows the steps needed fordetermining a reference clock phase signal which are performed in aphase correction device 307 according to an exemplary embodiment of thepresent invention.

[0044] The flow chart shown in FIG. 4 explains how the phase correctiondevice 307 determines the phase correction value 111.

[0045] To determine the phase deviation 111 a, the difference betweenthe edge position signal 309 and the control target value 310 is formed.

[0046] The processing then proceeds to a step S402 in which the lastdetected data transition is determined. It shall be assumed that thedata transition determined in the preceding step was a 0/1 datatransition or a 1/0 data transition, i.e. a single-step data transition.If the last detected data transition is also a 0/1 or 1/0 datatransition, the phase deviation 111 a is used directly as phasecorrection value 111 and the processing proceeds to an output step S403.

[0047] If it is determined that the last detected data transmission isnot a 0/1 or 1/0 data transition, the processing proceeds to a phasecorrection value determining step S404 in which a phase correction value111, determined as above, is taken into consideration in the calculationof the reference clock phase signal in that, in the case of a −1/1 datatransition 102, for example, the phase correction offset 111 b is addedto the phase deviation 111 a in a subsequent correction step S405. Theprocessing then proceeds to the output step S403.

[0048] It can be seen clearly that the flow chart shown in FIG. 4 iscorrespondingly provided if a preceding data transition was adouble-step data transition and is compared with a last detected datatransition. In this case, the interrogation in an interrogating stepS406 changes to the effect that an interrogation “0/1 or 1/0 datatransition?” is replaced by an interrogation “−1/1 or 1/−1 datatransition?”, i.e. the question is whether there is a double-step datatransition present instead of a single-step data transition.

[0049] It is also possible to relate the interrogation shown in FIG. 4to at least one arbitrary past data transition.

[0050] Although the present invention has been described above by meansof preferred exemplary embodiments, it is not restricted these but canbe modified in many ways.

[0051] List of Reference Designations

[0052]101 0/1 data transition

[0053]101 a 1/0 data transition

[0054]102 −1/1 data transition

[0055]103 0/−1 data transition

[0056]103 a −1/0 data transition

[0057]104 1/−1 data transition

[0058]105 baseline value

[0059]106 maximum data stream value

[0060]107 minimum data stream value

[0061]108 threshold value

[0062]109 0/1 threshold intersection point

[0063]110 −1/1 threshold intersection point

[0064]111 phase correction value

[0065]111 a phase deviation

[0066]111 b phase correction offset

[0067]301 digital datastream

[0068]302 datastream receiver

[0069]303 low-pass filter device

[0070]304 edge position detection device

[0071]305 low-pass-filtered datastream

[0072]306 threshold setting device

[0073]307 phase correction device

[0074]308 reference clock phase signal

[0075]309 edge position signal

[0076]310 target time of the control system

[0077] S401 input step

[0078] S402 data transition determining step

[0079] S403 output step

[0080] S404 phase correction value determining step

[0081] S405 correction step

[0082] S406 interrogation step

1. A method for recovering a digital datastream (301) in which areference clock phase (308) is recovered from the digital datastream(301), comprising the following steps: a) receiving the digitaldatastream (301) in a datastream receiver (302); b) optional low-passfiltering of the received digital datastream (301) in a low-pass filterdevice (303); c) setting a threshold value (108) in a threshold settingdevice (306); d) determining an edge position signal (309) by comparingan amplitude of the low-pass-filtered datastream (305) with thethreshold value (108) in an edge position detection device (304); e)determining a phase deviation (111 a) from a time difference between a0/1 threshold intersection point (109) of the threshold value (108) witha 0/1 data transition (101) or a −1/1 threshold intersection point (110)of the threshold value (108) with a −1/1 data transition (102) and thetarget time of the control system (310); f) correcting the phasedeviation (111 a) with the phase correction offset (111 b) in the phasecorrection device (307); and g) outputting a reference clock phasesignal (308) from the phase correction device (307).
 2. The method forrecovering a digital datastream (301) as claimed in claim 1, wherein thethreshold value (108) is located between a minimum datastream value(107) and a maximum datastream value (106).
 3. The method for recoveringa digital datastream (301) as claimed in one or both of claims 1 and 2,wherein the phase correction value (111) is provided both for positivethreshold values (108) which assume a value between a baseline value(105) and a maximum datastream value (106) and for negative thresholdvalues (108) which assume a value between the baseline value (105) and aminimum datastream value (107).
 4. The method for recovering a digitaldatastream (301) as claimed in one or more of claims 1 to 3, wherein thethreshold value (108) is set in such a manner that it assumes a valuebetween a baseline value (105) (logical “0”) and a maximum datastreamvalue (106) (logical “1”).
 5. The method for recovering a digitaldatastream (301) as claimed in one or more of claims 1 to 4, wherein thethreshold value (108) is set in such a manner that it assumes a valuebetween a baseline value (105) (logical “0”) and a minimum datastreamvalue (107) (logical “−1”).
 6. The method for recovering a digitaldatastream (301) as claimed in one or more of claims 1 to 5, wherein thethreshold value (108) is provided so as to be variably adjustable. 7.The method for recovering a digital datastream (301) as claimed in oneor more of claims 1 to 6, wherein the received digital datastream (301)is low-pass-filtered with a predeterminable cut-off frequency in alow-pass filter device (303).
 8. The method for recovering a digitaldatastream (301) as claimed in one or more of claims 1 to 7, wherein anabsolute value of a phase correction offset (111 b) is provided independence on a cut-off frequency of low-pass filter device (303), ofthe transmission channel and of the predeterminable threshold value(108).
 9. The method for recovering a digital datastream (301) asclaimed in one or more of claims 1 to 8, wherein an edge slope of a datatransition in the digital datastream (301) is calculated and the edge isallocated to a preceding data transmission in accordance with thegreatest similarity.
 10. The method for recovering a digital datastream(301) as claimed in one or more of claims 1 to 9, wherein the in eachcase preceding data transition is provided for determining an edgeposition signal (309) of a last detected data transition.
 11. The methodfor recovering a digital datastream (301) as claimed in one or more ofclaims 1 to 9, wherein the trend of the last control error is providedfor determining an edge position signal (309) of a last detected datatransition.
 12. The method for recovering a digital datastream (301) asclaimed in one or more of claims 1 to 10, wherein an arbitrary precedingdata transition (n−2, n−3, . . . ), where n is the last detected datatransition, is provided for determining an edge position signal (309) ofa last detected data transition.
 13. The method for recovering a digitaldatastream (301) as claimed in one or more of claims 1 to 11, wherein avariable threshold value (108) is provided which is derived from a peakamplitude of the datastream (301) by multiplying the peak amplitude ofthe datastream (301) by a predeterminable factor of less than
 1. 14. Adevice for recovering a digital datastream (301), comprising: a) adatastream receiver (302) for detecting the digital datastream (301); b)a low-pass filter device (303) for low-pass filtering of the detecteddigital datastream (301); c) a threshold setting device (306) forsetting a threshold value (108); d) an edge position detection device(304) for determining an edge position signal (309) by comparing anamplitude of the low-pass filtered datastream (305) with the thresholdvalue (108); and e) a phase correction device (307) for determining aphase deviation (111 a) from a time difference between a 0/1 thresholdintersection point (109) of the threshold value (108) with a 0/1 datatransition (101) or a −1/1 threshold intersection point (110) of thethreshold value (118) with a −1/1 data transition (102) and the targettime of the control system (310), and for correcting the first deviation(111 a) with the phase correction offset (111 b).